1. Field of the Invention
The present invention generally relates to a semiconductor device and a fabrication method thereof and, more particularly, to a method of fabricating a gate flash memory for increasing a coupling ratio between a floating gate and a control gate.
2. Background of the Related Art
A flash memory generally includes a floating gate and a control gate. A dielectric layer such as oxide-nitride-oxide (hereinafter referred to as “ONO”) is positioned between the floating gate and the control gate and a tunneling oxide is positioned between the control gate and a silicon substrate. Such a flash memory usually stores or removes data in the way that electrons or holes are held in or removed from the floating gate. In other words, because the floating gate is completely isolated by the tunneling oxide and the dielectric layer, once electrons or holes enter the floating gate, they cannot escape from the floating gate even if no power is supplied. Therefore, data can be stored in the flash memory.
In order to write or erase data in the flash memory, a bias applied to terminals accessible from outside, that is, the control gate and a junction or a substrate, has to be induced to the floating gate to generate a strong electric field at both ends of the tunneling oxide. A coupling ratio (hereinafter referred to as “CR”) is a ratio of the voltage applied to the control gate and the junction or the substrate and the voltage induced to the floating gate. As the coupling ratio, CR, increases, the efficiency of programming and erase operations in a memory cell improves and the voltage required from outside decreases.
The CR is defined as a ratio between tunneling oxide capacitance and ONO capacitance. When the tunneling oxide capacitance is represented as CTUN and the ONO capacitance is represented as CONO, the coupling ratio CR is expressed as follows:CR=CONO/(CTUN+CONO)
For a high CR, the CONO has to be relatively high compared to the CTUN. The capacitance is determined by several factors such as a dielectric constant, the thickness of a dielectric layer, and the area of a capacitor.
In a general flash memory fabrication process, the thickness of the tunneling oxide is about 80 Å through 120 Å and the thickness of the dielectric layer is about 150 Å through 300 Å. For same area of the CONO and the CTUN, the CONO becomes smaller than the CTUN and, therefore, it is difficult to obtain a CR required for adequate operation of the flash memory. Accordingly, in order to ensure a high CR, methods for increasing the surface area of the floating gate have been suggested.
FIGS. 1a through 1g are cross-sectional views illustrating a related art flash memory fabricating process for increasing the surface area of the floating gate.
Referring to FIG. 1a, a tunneling oxide layer 2 is deposited on a substrate 1. A first polysilicon layer 3 used to form a floating gate is then deposited on the tunneling oxide 2. Then, a first mask layer 4 is deposited on the first polysilicon layer 3. The first mask layer 4 is generally nitride.
Referring to FIG. 1b, some parts of the first mask layer 4, the first polysilicon layer 3, the tunneling oxide 2, and the silicon substrate 1 within a field oxide area 5 to be formed in a subsequent process are removed by a photolithography process and an etching process to form shallow trench isolation (hereinafter referred to as “STI”).
Referring to FIG. 1c, a field oxide 6 is deposited on the first mask layer 4 and the STI and a chemical mechanical polishing (hereinafter referred to as “CMP”) process is then performed so that the field oxide 6 remains only within the STI.
Referring to FIG. 1d, the STI field oxide 6 is etched until its height reaches the height of the floating gate 3, and then the first mask layer 4 is removed. Then, a second polysilicon layer 7 used to form a second floating gate is deposited over the whole surface of the resulting substrate including the first floating gate 3. A second mask layer is deposited on the second polysilicon layer 7 and selectively etched to form a second mask pattern 8.
Referring to FIG. 1e, a third mask material layer is deposited on the second polysilicon layer 7 and the second mask pattern 8, and anisotropically etched to form spacers 9 on the sidewalls of the second mask pattern 8.
Referring to FIG. 1f, the second polysilicon layer 7 is etched using the second mask pattern 8 and the spacers 9 as a hard mask to form the second floating gate 7. Then, the second mask pattern 8 and the spacers 9 are respectively removed.
Finally, referring to FIG. 1g, a dielectric layer 10 and a third polysilicon layer 11 used to form a control gate are deposited in order over the whole surface of the resulting structure.
In the above-mentioned art, the length of the floating gate is extended on the field oxide to increase the surface area of the floating gate. In addition, in order to minimize an increase in memory cell size due to the lengthened floating gate, the space between floating gates is minimized by a hard mask process. Thus, as shown in FIG. 1g, the area of the floating gate increases by 2(L+h) per cell compared to that of the tunneling oxide.
However, the related art flash memory fabricating methods are very complicated and have difficulty in obtaining a desired capacitance in addition to a high degree of integration. In addition, in three-dimensionally formed floating gates, an increase in the surface area between the floating gate and the substrate detrimentally affects program and erase operations. Therefore, the area between the floating gate and the control gate should be large while the area between the floating gate and the substrate is maintained constant.
In addition, in the related art, because the capacitance which affects the CR is determined by just the area of the floating gate and the side area of the floating gate along the word line, the coupling ratio is at most about 0.6. As a result, the voltage delivery efficiency from the control gate to the floating gate is poor, thereby requiring complicated source and drain structure and additional charge pumps to boost the voltage applied to the control gate.